The present invention claims priority from Japanese Patent Application No. 9-146694 filed Jun. 4, 1997, which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a data transform between two digital data signals having different sampling frequencies. The present invention can be utilized in a digital signal communication apparatus such as a portable telephone set.
2. Description of Related Art
Japanese Patent Application Laid-open No. Hei 4-245728 discloses a digital signal processor for transforming a digital data signal having a sampling frequency into a digital data signal having a sampling frequency different from that of the original digital data signal, in which a buffer is used to perform a read and a write operations at mutually different clock frequencies, respectively. A construction of the disclosed digital signal processor is shown in FIG. 1.
The conventional digital signal processor comprises a transmission line interface circuit 201, a clock extracting circuit 202, a sync circuit 203, a buffer 204, a clock generator 205, a control clock generator circuit 206, a slip control circuit 208, a PCM-FDM transformer circuit 207, an interpolation filter circuit 209 and a re-sampling circuit 210. A time-division multiplexed PCM signal input from the PCM transmission line is input to the transmission line interface circuit 201 through a data input terminal 211. The PCM signal is transformed in the transmission line interface circuit 201 from a bipolar signal into a unipolar signal. Thereafter, the unipolar signal is frame-synchronized in the sync circuit 203 by using a clock extracted from the unipolar signal by the clock extractor circuit 202. Further, the frame synchronized unipolar signal is sampled to an N-time sampling data (8.times.N kHz sample) in the interpolation filter circuit 209 and output to the buffer 204. The PCM signal is written in a memory of the buffer 204 with using the clock from the clock extractor circuit 202 and the frame sync signal from the sync circuit 203. The PCM signal having sampling frequency of 8.times.N kHz and written in the buffer 204 is read out by using the clock output from the clock generator circuit 205 and a signal from the control clock circuit 206. Only 8 kHz sampling value of the signal thus read out is extracted by the re-sampling circuit 210. The extracted PCM signal is transformed into an FDM signal by the PCM-FDM transformer circuit 207 and then output from a data output terminal 212.
Assuming that the write speed of the PCM signal in the buffer 204 is different from the read speed thereof, that is, the write and read operations are performed with clocks having mutually different frequencies, the memory of the buffer 204 overflows or underflows, causing the so-called data slip which is drop out of the PCM signal to occur. Therefore, the slip control circuit 208 prevents overflow or underflow of the buffer memory from occurring and hence the data slip from occurring, by comparing in phase the frame sync signal from the sync circuit 203 with the frame sync signal from the control clock generator circuit 206 and stopping the write or read operation with respect to the memory of the buffer 204 for a time corresponding to one frame. Further, the data sampled at 8.times.N kHz is written in the buffer 204 by the interpolation filter circuit 209 and is transformed into the data sampled at 8 kHz by the re-sampling circuit 210. Therefore, even if data loss occurs due to data slip, a time deviation due to the drop out of the PCM signal is small compared with the case where the data is merely sampled at 8 kHz, and thus impulse noise is reduced.
However, when there is a jitter, that is, fluctuation of frequency, in the clock extracted by the clock extractor circuit 202 or the clock output from the control clock generator circuit 206 of the conventional system mentioned above, data in the vicinity of the timing at which data slip may occur is detected as a phase shift of the frame synchronization, on which unnecessary (erroneous) data interpolation is executed. With such unnecessary data interpolation, there may be data discontinuity or noise due to data discontinuity occurs. Particularly, in a case of narrow band signal such as sine wave signal, considerable noise may occur.